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M5CAARCH-RM/D Datasheet(PDF) 91 Page - NXP Semiconductors |
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M5CAARCH-RM/D Datasheet(HTML) 91 Page - NXP Semiconductors |
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91 / 114 page ![]() AC Timing Specifications 91 03 MDIO Serial Interface Timing Specifications The MDIO serial interface timing is shown in Figure 20 and described in Table 49. Figure 20 MDIO Serial Interface Timing Diagram Cycle 2 Cycle 3 Cycle 4 Tsic Tsids SICL SIDA (output) SIDA (input) Tsods Tsodh Table 49 MDIO Serial Interface Timing Description SYMBOL PARAMETER MIN TYP MAX UNIT Tsic SICL Cycle Time 40 ns Tsids SIDA Input Setup 10 ns Tsidh SIDA Input Hold 0.0 ns Tsods SIDA Output Setup 10 ns Tsodh SIDA Output Hold 10 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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