93LC86ATESTG datasheet(11/28 Pages) MICROCHIP

No. de pieza	93LC86ATESTG

Descripción Electrónicos	16K Microwire Compatible Serial EEPROM

PDF	28 Pages

Scroll/Zoom	100%

Fabricante Electrónico	MICROCHIP [Microchip Technology]

Página de inicio	http://www.microchip.com

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11 / 28 page

DS21797G-page 11

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

2.9

Write All (WRAL)

The Write All (WRAL) instruction will write the entire

memory array with the data specified in the command.

The self-timed auto-erase and programming cycle is

initiated by the rising edge of CLK on the last data bit.

Clocking of the CLK pin is not necessary after the

device has entered the WRAL cycle. The WRAL

command does include an automatic ERAL cycle for

the device. Therefore, the WRAL instruction does not

require an ERAL instruction, but the chip must be in the

EWEN status.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

VCC must be

≥ 4.5V for proper operation of WRAL.

FIGURE 2-7:

WRAL TIMING

Note:

The write sequence requires a logic high

signal on the PE pin prior to the rising

edge of the last data bit.

Note:

After the Write All cycle is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

High-Z

•••

High-Z

Busy

Ready

TWL

TCSL

TSV

TCZ

93LC86ATESTG Datasheet(PDF) 11 Page - Microchip Technology