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ST20-GP6 Datasheet(PDF) 92 Page - STMicroelectronics |
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ST20-GP6 Datasheet(HTML) 92 Page - STMicroelectronics |
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92 / 123 page  ST20-GP6 92/123 ASCIntEnable register The ASCIntEnable register enables a source of interrupt. Interrupts will occur when a status bit in the ASCStatus register is 1, and the corresponding bit in the ASCIntEnable register is 1.* ASCIntEnable ASC base address + #10 Read/Write Bit Bit field Function 0 RxBufFullIE Receiver buffer full interrupt enable 1 TxEmptyIE Transmitter empty interrupt enable 2 TxHalfEmptyIE Transmitter buffer half empty interrupt enable 3 ParityErrorIE Parity error interrupt enable 4 FrameErrorIE Framing error interrupt enable 5 OverrunErrorIE Overrun error interrupt enable 6 TimeoutNotEmpty IE Timeout not empty interrupt enable 7 TimeoutIdleIE Timeout idle interrupt enable 8 RxHalfFullIE Receiver buffer half full interrupt enable 15:9 RESERVED. Write 0, will read back 0. Table 15.5 ASCIntEnable register format |
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