September 1993

13

Philips Semiconductors

Product specification

5-Bit x 64-word FIFO register; 3-state

74HC/HCT7404

With FIFO full; SI held HIGH in anticipation of empty location

Notes to Fig.8

1. FIFO is initially full, shift-in is held HIGH

2. SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins

3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input

4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again

5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.

Fig.8 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.

handbook, full pagewidth

SI INPUT

MGA660

34

DIR OUTPUT

VM

(1)

2

bubble - up

delay

VM

(1)

5

SO INPUT

t PLH

VM

(1)

1

t W

(1) HC

:

HCT :