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LTC2422CMS Datasheet(PDF) 21 Page - Linear Technology

No. de pieza LTC2422CMS
Descripción Electrónicos  1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10
PDF  32 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
Logo LINER - Linear Technology

LTC2422CMS Datasheet(HTML) 21 Page - Linear Technology

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LTC2421/LTC2422
24212f
APPLICATIO S I FOR ATIO
Figure 12. Internal Serial Clock, Autostart Operation
VCC
FO
FSSET
ZSSET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
0V TO FSSET – 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
µF
110
9
8
7
6
CEXT
2
3
4
5
2.7V TO 5.5V
LTC2422
VCC
VCC
10k
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
SDO
Hi-Z
Hi-Z
SCK
(INTERNAL)
CS
VCC
GND
2420 F12
BIT 0
SIG
BIT 21
BIT 22
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
EOC
BIT 23
Figure 13. CS Capacitance vs tSAMPLE
Figure 14. CS Capacitance
vs Output Rate
CAPACITANCE ON CS (pF)
1
5
6
7
1000
10000
24212 F13
4
3
10
100
100000
2
1
0
VCC = 5V
VCC = 3V
CAPACITANCE ON CS (pF)
1
0
50
100
150
200
250
300
10
100
1000
10000
24212 F15
100000
VCC = 5V
VCC = 3V
to take advantage of exceptional accuracy and low supply
current.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
In order to preserve the LTC2421/LTC2422’s accuracy, it
is very important to minimize the ground path impedance
which may appear in series with the input and/or reference
signal and to reduce the current which may flow through
this path. The GND pin should be connected to a low
CAPACITANCE ON CS (pF)
1
0
50
100
150
200
250
300
10
100
1000
10000
24212 F15
100000
VCC = 5V
VCC = 3V
Figure 15. CS Capacitance
vs Supply Current



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