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LTC2421IMS Datasheet(PDF) 13 Page - Linear Technology

No. de pieza LTC2421IMS
Descripción Electrónicos  1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10
PDF  32 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
Logo LINER - Linear Technology

LTC2421IMS Datasheet(HTML) 13 Page - Linear Technology

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LTC2421/LTC2422
24212f
APPLICATIO S I FOR ATIO
As long as the voltage on the VIN pin is maintained within
the – 0.3V to (VCC + 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from – 0.125 • VREF to 1.125 • VREF. For input voltages
greater than 1.125 • VREF, the conversion result is clamped
to the value corresponding to 1.125 • VREF. For input volt-
ages below – 0.125 • VREF,theconversionresultisclamped
to the value corresponding to – 0.125 • VREF.
Frequency Rejection Selection (FO Pin Connection)
The LTC2421/LTC2422 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz
±2% or 60Hz ±2%. For
60Hz rejection, FO (Pin 10) should be connected to GND
(Pin 6) while for 50Hz rejection the FO pin should be con-
nected to VCC (Pin 1).
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2421/
LTC2422 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the FO pin and turns off the internal
oscillator. The frequency fEOSC of the external signal must
be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC,theLTC2421/LTC2422providebetterthan
110dB normal mode rejection in a frequency range fEOSC/
2560
±4% and its harmonics. The normal mode rejection
as a function of the input frequency deviation from fEOSC/
2560 is shown in Figure 5.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2421/
LTC2422 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state or
during the data output state while the converter uses an
Table 2. LTC2421/LTC2422 Output Data Format
Bit 23
Bit 22*
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
…
Bit 0
Input Voltage
EOC
CH0/CH1
SIG
EXR
MSB
LSB
VIN > 9/8 • VREF
0
CH0/CH1
1100
0
1
1
...
1
9/8 • VREF
0
CH0/CH1
1100
0
1
1
...
1
VREF + 1LSB
0
CH0/CH1
1100
0
0
0
...
0
VREF
0
CH0/CH1
1011
1
1
1
...
1
3/4VREF + 1LSB
0
CH0/CH1
1011
0
0
0
...
0
3/4VREF
0
CH0/CH1
1010
1
1
1
...
1
1/2VREF + 1LSB
0
CH0/CH1
1010
0
0
0
...
0
1/2VREF
0
CH0/CH1
1001
1
1
1
...
1
1/4VREF + 1LSB
0
CH0/CH1
1001
0
0
0
...
0
1/4VREF
0
CH0/CH1
1000
1
1
1
...
1
0+/0–
0
CH0/CH1
1/0**
0
0
0
0
0
0
...
0
–1LSB
0
CH0/CH1
0111
1
1
1
...
1
–1/8 • VREF
0
CH0/CH1
0111
1
0
0
...
0
VIN < –1/8 • VREF
0
CH0/CH1
0111
1
0
0
...
0
*Bit 22 is always 0 for the LTC2421 **The sign bit changes state during the 0 code.



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