UPSD325X datasheet(102/176 Pages) STMICROELECTRONICS

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µPSD325X DEVICES

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PSD MODULE

The PSD Module provides configurable

Program and Data memories to the 8032 CPU

core (MCU). In addition, it has its own set of I/O

ports and a PLD with 16 macrocells for general

logic implementation.

Ports A,B,C, and D are general purpose

programmable I/O ports that have a port

architecture which is different from the I/O ports

in the MCU Module.

The PSD Module communicates with the MCU

Module through the internal address, data bus

(AO-A15, DO-D7) and control signals (RD, WR,

PSEN, ALE, RESET). The user defines the

Decoding PLD in the PSDsoft Development

Tool and can map the resources in the PSD

Module to any program or data address space.

Figure 50 shows the functional blocks in the

PSD Module.

Functional Overview

1 or 2 Mbit Flash memory. This is the main

Flash memory. It is divided into eight equal-

sized blocks that can be accessed with user-

specified addresses.

Secondary 256 Kbit Flash boot memory. It is

divided into four equal-sized blocks that can be

accessed with user-specified addresses. This

secondary memory brings the ability to execute

code and update the main Flash

concurrently.

256 Kbit SRAM. The SRAM’s contents can be

protected from a power failure by connecting an

external battery.

CPLD with 1G Output Micro Cells (OMCs} and

24 Input Micro Cells (IMCs). The CPLD may be

used to efficiently implement a variety of logic

functions for internal and external control.

Examples include state machines, loadable

shift registers, and loadable counters.

Decode PLD (DPLD) that decodes address for

selection of memory blocks in the PSD Module.

Configurable I/O ports (Port A,B,C and D) that

can be used for the following functions:

– MCU I/Os

–PLD I/Os

– Latched MCU address output

– Special function I/Os.

– I/O ports may be configured as open-drain

outputs.

Built-in JTAG compliant serial port allows full-

chip In-System Programmability (ISP). With it,

you can program a blank device or reprogram a

device in the factory or the field.

Internal page register that can be used to

expand the 8032 MCU Module address space

by a factor of 256.

Internal programmable Power Management

Unit (PMU) that supports a low-power mode

called Power-down Mode. The PMU can

automatically detect a lack of the 8032 CPU

core activity and put the PSD Module into

Power-down Mode.

Erase/WRITE cycles:

– Flash memory - 100,000 minimum

– PLD - 1,000 minimum

– Data Retention: 15 year minimum (for Main

Flash memory, Boot, PLD and Configuration

bits)

UPSD325X Datasheet(PDF) 102 Page - STMicroelectronics

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