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Page 2 of 4

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Rev 1.0

17/02/2023

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS

VCC = 5V

3.0

3.6

4.3

V

VCC = 10V

6.0

6.8

8.6

V

Positive Going Threshold Voltage

VT+

VCC = 15V

9.0

10.0

12.9

V

VCC = 5V

0.7

1.4

2.0

V

VCC = 10V

1.4

3.2

4.0

V

Negative Going Threshold Voltage

VT-

VCC = 15V

2.1

5.0

6.0

V

VCC = 5V

1.0

2.2

3.6

V

VCC = 10V

2.0

3.6

7.2

V

Hysteresis

VT+ - VT-

VCC = 15V

3.0

5.0

10.8

V

VCC = 5V, IO = -10µA

4.5

-

-

V

Logical “1” Output Voltage

VOUT(1)

VCC = 10V, IO = -10µA

9.0

-

-

V

VCC = 5V, IO = 10µA

-

-

0.5

V

Logical “0” Output Voltage

VOUT(0)

VCC = 10V, IO = 10µA

-

-

1.0

V

Logical “1” Input Current

IIN(1)

VCC = 15V, VIN = 15V

-

0.005

1.0

µA

Logical “0” Input Current

IIN(0)

VCC = 15V, VIN = 0V

-1.0

-0.005

-

µA

Supply Current

ICC

VCC =15V,VIN=0V/15V

-

0.05

15

µA

VCC = 5V, VIN = 2.5V

-

20

-

µA

VCC = 10V, VIN = 5V

-

200

-

µA

Supply Current

2

ICC

VCC = 15V, VIN = 7.5V

-

600

-

µA

CMOS/LPTTL INTERFACE

Logical “1” Input Voltage

VIN(1)

VCC = 5V

4.3

-

-

V

Logical “0” Input Voltage

VIN(0)

VCC = 5V

-

-

0.7

V

Logical “1” Output Voltage

VOUT(1)

VCC= 4.75V,IO= -360µA

2.4

-

-

V

Logical “0” Output Voltage

VOUT(0)

VCC =4.75V, IO = 360µA

-

-

0.4

V

OUTPUT DRIVE CURRENT TA = 25°C

VCC = 5V, VOUT = 0V

-1.75

-3.3

-

mA

Output Source Current

(P-Channel)

ISOURCE

VCC = 10V, VOUT = 0V

-8.0

-15

-

mA

VCC = 5V, VOUT = VCC

1.75

3.6

-

mA

Output Source Current

(N-Channel)

ISINK

VCC = 10V, VOUT = VCC

8.0

16

-

mA

DYNAMIC ELECTRICAL CHARACTERISTICS

3 T

A = 25°C, CL = 50pF unless otherwise stated

VCC = 5V

-

220

400

ns

Propagation Delay

from Input to Output

tPD0,

tPD1

VCC = 10V

-

80

200

ns

Input Capacitance

CIN

Any Input

-

5.0

-

pF

Power Dissipation Capacitance

4

CPD

Per Gate

-

20

-

pF

DC Electrical Characteristics T

A = -40 to +85°C unless otherwise stated

2. Only one of the six inputs is at ½ VCC; the others are either at VCC or GND. 3. Not production tested in die form, characterized by chip design.

4. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

CMOS High Voltage Logic – MM74C14N