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EM6607 Datasheet(PDF) 4 Page - EM Microelectronic - MARIN SA |
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EM6607 Datasheet(HTML) 4 Page - EM Microelectronic - MARIN SA |
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4 / 47 page ![]() R EM6607 Copyright © 2005, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com Table of Tables Table 1. IntRq register 83H 7 Table 2. Watchdog register - WD 84H 8 Table 3. Internal state in Active, Stand-by and Sleep mode 85H 8 Table 4. PortA Inputs RESET options (metal Hardware option) 86H 10 Table 5. Watchdog-Timer Option (software option) 87H 10 Table 6. Software Power-On-Reset 88H 10 Table 7. Initial Value after RESET 89H 11 Table 8. Prescaler interrupts source 90H 12 Table 9. Prescaler control register - PRESC 91H 12 Table 10. Watchdog register - WD 92H 12 Table 11. Input / Output Ports Overview 93H 13 Table 12. Option register - Option 94H 13 Table 13. PortA input status register - PortA 95H 14 Table 14. PortA Interrupt request register - IRQpA 96H 14 Table 15. PortA interrupt mask register - MportA 97H 14 Table 16. PortB input/output status register - PortB 98H 15 Table 17. PortB Input/Output control register - CIOportB 99H 15 Table 18. Ports A&C Interrupt 100H 16 Table 19. PortC input/output register - PortC 101H 16 Table 20. PortC Interrupt request register - IRQpC 102H 16 Table 21. PortC interrupt mask register - MportC 103H 16 Table 22. Option2 register - Option2 104H 17 Table 23. PortD Input/Output register - PortD 105H 18 Table 24. Ports control register - CPIOB 106H 18 Table 25. PortE Input/Output status register - PortE 107H 19 Table 26. PortE Input/Output control register - CIOPortE 108H 19 Table 27. Buzzer control register - BEEP 109H 20 Table 28. Buzzer output pad allocation 110H 20 Table 29. PB0 & PE0 function used with BUen and BuzzerPE0 control bits 111H 20 Table 30. Timer Clock Selection 112H 22 Table 31. Timer control register - TimCtr 113H 22 Table 32. LOW Timer Load/Status register - LTimLS (4 low bits) 114H 22 Table 33. HIGH Timer Load/Status register - HTimLS (4 high bits) 115H 22 Table 34. PA3 counter input selection register - PA3cnt 116H 22 Table 35. PA3 counter input selection 117H 22 Table 36. Main Interrupt request register - IntRq (Read Only)* 118H 23 Table 37. Register - CIRQD 119H 24 Table 38. SVLD Level selection 120H 25 Table 39. SVLD control register - SVLD 121H 25 Table 40. SWB clock selection 122H 26 Table 41. SWB clock selection register - ClkSWB 123H 26 Table 42. PortD status 124H 26 Table 43. SWB buffer register - SWbuff 125H 27 Table 44. SWB Low size register - LowSWB 126H 27 Table 45. SWB High size register – HighSWB 127H 27 Table 46. input/output Ports 128H 31 Table 47. PortB Hi Current Drive capability 129H 31 |
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