Philips Semiconductors

Product specification

74F322

8-bit serial/parallel register with sign extend (3-State)

1

1988 Apr 22

853-0366 93020

FEATURES

DESCRIPTION

The 74F322 is an 8-bit shift register with provision for either serial or

parallel loading and with 3-State parallel outputs plus a bi-state

serial output. Parallel data inputs and outputs are multiplexed to

minimize pin count. State changes are initiated by the rising edge of

the clock. Four synchronous modes of operation are possible: hold

(store), shift right with serial entry, shift right with sign extend, and

parallel load. An asynchronous Master Reset (MR) input overrides

clocked operation and clears the registers.

The 74F322 contains eight D-type edge triggered flip-flops and the

interstage gating required to perform right shift and the intrastage

gating necessary for hold and synchronous parallel load operations.

A Low signal on RE enables shifting or parallel loading, while a High

signal enables the hold mode. A High signal on S/P enables shift

right, while a Low signal disables the 3-State output buffers and

enables parallel loading. In the shift right mode a High signal on SE

enables serial entry from either D0 or D1, as determined by the S

input. A Low signal on SE enables shift right, but Q7 reloads its

contents, thus performing the sign extend function. A High signal on

OE disables the 3-State output buffers, regardless of the other

control inputs. In this condition the shifting and loading operations

can still be performed.

PIN CONFIGURATION

20

19

18

17

16

15

14

13

12

10

11

9

8

7

6

5

4

3

2

1

VCC

S

SE

D1

I/O7

I/O5

I/O3

I/O1

CP

RE

I/O6

I/O4

I/O2

I/O0

OE

S/P

D0

MR

GND

Q7

SF00874

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F322

125MHz

60mA

ORDERING INFORMATION

DESCRIPTION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

20-pin plastic DIP

N74F322N

20-pin plastic SOL

N74F322D

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0, D1

Serial data inputs

1.0/1.0

20

µA/0.6mA

S

Serial data select input

1.0/2.0

20

µA/1.2mA

SE

Sign Extend input

1.0/3.0

20

µA/1.8mA

CP

Clock Pulse input (Active rising edge)

1.0/1.0

20

µA/0.6mA

S/P

Serial (High) or Parallel (Low) mode control input

1.0/1.0

20

µA/0.6mA

RE

Register Enable input (Active Low)

1.0/1.0

20

µA/0.6mA

MR

Asynchronous Master Reset input (Active Low)

1.0/1.0

20

µA/0.6mA

OE

Output Enable input (Active Low)

1.0/1.0

20

µA/0.6mA

Q7

Bi-state serial output

50/33

1.0mA/20mA

I/On

Multiplexed parallel data inputs or

3.5/1.0

70

µA/0.6mA

I/On

3-State parallel outputs

150/40

3.0mA/24mA

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20

µA in the High State and 0.6mA in the Low state.