74F280 datasheet(2/8 Pages) PHILIPS

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Philips Semiconductors

Product specification

74F280B

9-bit odd/even parity generator/checker

1996 Mar 12

853-0363 16555

FEATURES

• High-impedance NPN base inputs for reduced loading

(20

µA in Low and High states)

• Buffered inputs — one normalized load

• Word length easily expanded by cascading

• Industrial temperature range available (–40°C to +85°C)

DESCRIPTION

The 74F280B is a 9-bit Parity Generator or Checker commonly used

to detect errors in high speed data transmission or data retrieval

systems. Both Even (

∑E) and Odd (∑O) parity outputs are available

for generating or checking even or odd parity on up to 9 bits.

The Even (

∑E) parity output is High when an even number of Data

inputs (I0 - I8) are High. The Odd (∑O) parity output is High when an

odd number of Data inputs are High.

Expansion to larger word sizes is accomplished by tying the Even

(

∑E) outputs of up to nine parallel devices to the data inputs of the

final stage. This expansion scheme allows an 81-bit data word to be

checked in less than 20ns.

PIN CONFIGURATION

VCC

ΣE

GND

ΣO

SF00849

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F280B

5.5ns

26mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

INDUSTRIAL RANGE

VCC = 5V ±10%,

Tamb = –40°C to +85°C

PKG. DWG. #

14-pin plastic DIP

N74F280BN

I74F280BN

SOT27-1

14-pin plastic SO

N74F280BD

I74F280BD

SOT108-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

I0 - I8

Data inputs

1.0/0.033

µA/20µA

∑E, ∑O

Parity outputs

50/33

1.0mA/20mA

NOTE:

One (1.0) FAST Unit Load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

10 11

12 13

ΣO

ΣE

I0 I1 I2 I3 I4 I5 I6 I7 I8

SF00845

IEC/IEEE SYMBOL

ΣO

ΣE

VCC=Pin 14

GND=Pin 7

SF00846

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