AD6472

–8–

REV. 0

80-Lead Metric Plastic Quad Flatpack

S-80A

SEATING

PLANE

0.134 (3.40)

MAX

0.041 (1.03)

0.029 (0.73)

0.004 (0.10)

MAX

0.120 (3.05)

0.100 (2.55)

0.010 (0.25)

MIN

0.015 (0.38)

0.009 (0.22)

0.690 (17.45)

0.667 (16.95)

0.555 (14.10)

0.547 (13.90)

1

20

21

41

40

60

61

80

0.486 (12.35) BSC

TOP VIEW

(PINS DOWN)

0.026 (0.65)

BSC

PCB Layout Recommendations

Analog and Digital

Separate the analog and digital grounds.

Ground Planes

Use a single 35 to 50 mil wide trace un-

der the device to connect the two ground

planes. Connect the IC ground pins

directly to the respective ground planes.

Power Supply

Use one 0.1

µF capacitor for each IC de-

Capacitors

coupling power supply connection in addi-

tion to capacitance shown in schematic.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

12ns

10ns

2

SCLK

SFRAME

SDATA

D6

MSB

D5

D4

D3

D2

D0

D1

X

XX

X

X

X

X

X

D6

MSB

D5

D4

1. THE RISING EDGE OF SFRAME CAN OCCUR ANYWHERE. SFRAME MUST BE AT LEAST ONE CLOCK CYCLE WIDE.

2. SFRAME FALLING EDGE MUST OCCUR BEFORE THE SCLK RISING EDGE THAT CAPTURED THE SERIAL LSB.

THIS ENSURES CORRECT LOADING INTO THE DAC.

FULL SCALE

MID-SCALE

MINIMUM

OUTPUT

1111111

1000000

0000000

WORD

VOLTAGE

4.5

2.5

0.5

1

THE FIRST 7 BITS OF THE 16-BIT SERIAL WORD ARE THE INPUT TO THE TR DAC, MSB FIRST. THE NUMBER

SYSTEM IS TWOS COMPLEMENT, AS FOLLOWS:

X

Figure 6. Timing Recovery DAC Converter Timing