7708 datasheet(17/42 Pages) POWERINT

17 / 42 page

Rev. B 04/15

TFS7701-7708

www.power.com

Figure 16. LM431 Feedback Loop Components.

Feedback Loop Design

The HiperTFS-II is a voltage-mode controller. The main forward

plant feedback loop poles and zeros are:

•

Output LC filter double pole – typically at 800 Hz, slightly

underdamped.

•

Output capacitor ESR zero – typically at 3-5 kHz.

•

Optocoupler and FEEDBACK pin system pole – typically at

8-12 kHz. (The HiperTFS-2 has a low impedance FEEDBACK

pin to improve optocoupler bandwidth)

See Figure 16, the compensator should have a:

•

Pole at the origin (an integrator to minimize steady-state error).

This is implemented by C9.

•

A Zero near the LC double pole location. This is implemented

by R21 in conjunction with C8.

•

A phase-boost circuit, centered near the crossover frequency

– implemented with R10 and C4. This will improve phase

margin and increase the crossover frequency.

With the above compensation, and with the use of low ESR

electrolytic capacitors, a gain crossover frequency of 7-9 kHz

with a gain margin of >55° is achievable.

Resistor R11 and C5 are for soft-start. They do not contribute

significantly to the gain-phase characteristic.

Resistor R15 should be sized to conduct approximately 10 mA

when the TL431 is fully “ON” or saturated ( 2.5 V on the cathode).

It is also an overall gain-setting resistor, affecting the entire

frequency range. It, along with the phase-boost network

(R10 + C4), are the main high-frequency gain setting components.

Resistor R38 is to provide the minimum bias current for the

LM431. Capacitor C9 rolls off the LM431 gain at very high

frequencies.

Overvoltage Protection

An overvoltage protection circuit can be implemented by sourcing

>15 mA into the BYPASS pin to cause latching shut-off of both

converters. Resetting requires the BYPASS pin voltage to fall

below 4.8 V.

PI-7013-050313

HiperTFS-2

Bad

Bulk

Capacitor

High Current

Trace with

Large di/dt

Optocoupler

To Other Small

Signal Parts

Good Good

Figure 17. The PCB Trace from the Bulk Capacitor to the SOURCE Pin Contains

Currents with Large di/dt. Do not Return any Small Signal Ground

Connections to this Trace, Such as Small Signal Bypass Capacitors,

or Optocouplers.

Layout Considerations

Source and Ground Pins

Connect SOURCE and GROUND pins together on the PCB. All

high current traces (e.g., from bulk capacitor), should route to

the SOURCE pin. All small signal traces, and low voltage

bypass capacitors, should be connected to the GROUND pin.

See Figure 17. If this rule is violated, the connection in question

must be very close to the SOURCE or GROUND pin.

Bypass Capacitors

The BYPASS pin and ENABLE pin bypass capacitors must be

connected with short traces to the GROUND pin. Likewise, the

VDDH bypass capacitor must be connected with short traces

to the HIGH-SIDE SOURCE pin.

Primary Return (B-) Routing for HiperTFS-2 and PFC MOSFET

When the HiperTFS-2 shares a heat sink with a HiperPFS or

other PFC MOSFET, there is potential for noise coupling to

cause misbehavior, due to the very high di/dt associated with

the PFC diode reverse recovery. The metal in the backside of

the HiperTFS-2 is internally connected to the SOURCE pin and

thus the heat sink will be at SOURCE pin potential. The heat

sink should not be used to conduct current. The HiperTFS-2

requires a dedicated PCB trace from the SOURCE pin to the

bulk capacitor B- pin. The HiperPFS (or PFC MOSFET Source)

requires a separate PCB trace to the bulk capacitor B- pin. The

bulk capacitor is preferably placed between the HiperPFS and

HiperTFS-2. The heat sink must have a single connection to the

PFC SOURCE pin, which must be as close as possible to the

PFC MOSFET. Because of the PFC’s higher di/dt, the bulk

capacitor should be closer to the PFC than to the HiperTFS-2.

See Figure 18.

Standby Primary Bias (V

AUX) Capacitor Ground Routing

The primary V

AUX output filter capacitor negative terminal should

be routed to the bulk capacitor B- terminal. This is to prevent

the large noise currents that flow during common-mode surge

and ESD, from flowing in the HiperTFS-2 small-signal PCB

ground traces and creating ground bounce issues.

µH

47 nF

50 V

47 nF

50 V

C10

1500

µF

16 V

C24

1500

µF

16 V

R21

3.3 k

Ω

LM431

R24

3.92 k

Ω

R15

1 k

Ω

R38

1 k

Ω

U1A

PC357A

15 k

Ω

R10

220

Ω

1 nF

100 V

RTN

+12 V

Main

47 nF

50 V

R11

39 k

Ω

PI-6999a-052313

7708 Datasheet(PDF) 17 Page - Power Integrations, Inc.

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