STPM32 datasheet(67/121 Pages) STMICROELECTRONICS

67 / 121 page

DS10272 Rev 8

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STPM32, STPM33, STPM34

Theory of operation

121

8.6

Communication protocol

A single communication session consists of 4 + 1 (optional CRC) bytes full-duplex data

sequence organized as follows:

The above information is exchanged between master and slave in the same communication

session, or transaction. SPI master can issue a read-request and a write-request (optional).

The master initiates the communication sending the STPM3x a frame see Table 24 (read

address - write address - LS data byte - MS data byte - optional CRC).

Two command codes are provided:



Dummy read address 0xFF increments by one the internal read pointer



Dummy write address 0xFF specifies that no writing is requested (the two following

incoming data frames are ignored)

Upon the reception of a frame, the STPM3x replies to master data sending the 32-bit

slave sends, by default, the 32-bit data stored into the first (row 0) memory register. Data are

organized in 8-bit packets so that the least significant byte is sent first and the most

significant byte is sent last.

A final 8-bit CRC packet is sent to master to verify no data corruption has occurred during

the transmission from slave to master. The CRC feature, enabled by default, can be

controlled by a configuration bit into US_REG1 memory row (read address 0x24, write

address 0x24).

If CRC bit in US_REG1 is cleared, the communication consists of 4 bytes only.

Write-requests are executed immediately after the transaction has completed, while read-

requests are fulfilled at the end of the next transaction only, because the sent read-address

has just set the internal register pointer to deliver data during the following transaction.

So, while one transaction is enough to write data into memory, at least two transactions are

needed to read selected data from memory.

Data bytes are swapped with respect to the order of the byte, since during transmission, the

3rd byte sent to MOSI line is the least-significant (LS) byte (bits [7:0]) and the 4th byte is the

most-significant (MS) byte of the data to be written (bits [15:8]).

On MISO line, the first data byte received is the least-significant (LS, bits [7:0]) and the last

is the most-significant (MS, bits [31:24]) of the record, as shown below.

Table 24. Communication session structures

Byte

Master-side transmitted data

Slave-side transmitted data

ADDRESS for 32-bit register to be read

Previously requested data byte LSB

ADDRESS for 16-bit register to be written Previously requested data byte 2 out of 4

DATA for 16-bit register to be written, LSB Previously requested data byte 3 out of 4

DATA for 16-bit register to be written, MSB Previously requested data byte MSB

5 (optional) Master CRC verification packet

Slave CRC verification packet

STPM32 Datasheet(PDF) 67 Page - STMicroelectronics

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