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ST7293C3B6 Datasheet(PDF) 13 Page - STMicroelectronics

No. de pieza ST7293C3B6
Descripción Electrónicos  8-BIT MCU WITH 6K ROM, EEPROM AND 16-BIT TIMER WITH INPUT CAPTURE AND DUAL OUTPUT COMPARE
PDF  69 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7293C3B6 Datasheet(HTML) 13 Page - STMicroelectronics

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ST7294
RESET (Continued)
Table 4. Actions caused by RESET, Power-on Reset (POR), WAIT and HALT
Note 1: As can be seen in Table 4 above, WAIT mode only disables the CPU clock and not the Timer clock.
Figure 10. External Reset Timing Diagram
ACTION
RESET
POR
WAIT
HALT
Timer Prescaler reset to 0
X
X
-
-
Timer Counter set to FFFCh
X
X
-
-
All Timer enable bits reset to 0 (disabled)
X
X
-
-
Data Direction Registers reset to 0 (i.e. all I/O bits set as inputs)
X
X
-
-
Stack Pointer set to 00FFh
X
X
-
-
Internal Address Bus forced to Restart Vector
X
X
-
-
Interrupt Mask Bit (I-Bit, CCR) set to 1 (Interrupt disabled)
X
X
-
-
Interrupt Mask Bit (I-Bit, CCR) reset to 0 (Interrupt enabled)
-
-
X
X
HALT Latch reset
X
X
-
-
INT Latch reset
X
X
-
-
WAIT Latch reset
X
X
-
-
CPU Clock disabled (for 4096 clock cycles)
-
X
-
X
CPU Clock disabled(1)
-X
X
X
Timer Clock disabled(1)
-X
-
X
SM bit cleared
X
X
-
X
Watchdog Counter Rest
X
X
-
X
Watchdog WDOG bit reset
X
X
-
X
EEPROM control bits reset
X
X
-
-
3FFEh
3FFF
t
RL
NEW PC
V
DD
CPU CLOCK
PC
CPU RESET
RESET
0V
OSC
VR02046B



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