KTB8331

December 2021

– Revision 04b

Page 15 of 25

Kinetic Confidential

Figure 2. Data Transfer on I2C Serial Bus

The KTB8331 7-bit slave device address is listed in the Ordering Information table in page 3.

There are two kinds of I2C data transfer cycles: write cycle and read cycle.

I2C Write Cycle

For I2C write cycle, data is transferred from a master to a slave. The first byte transmitted is the 7-bit slave

address

plus one bit of ‘0’ for write. Next follows a number of data bytes. The slave returns an acknowledge bit

after each received byte. Data is transferred with the most significant bit (MSB) first. Figure 3 shows the sequence

of the I2C write cycle.

Figure 3. I2C Write Cycle

I2C Write Cycle Steps:

• Master generates start condition.

• Master sends 7-bit slave address and 1-bit data direction ‘0’ for write.

• Slave sends acknowledge if the slave address is matched.

• Master sends 8-bit register address.

• Slave sends acknowledge.

• Master sends 8-bit data for that addressed register.

• Slave sends acknowledge.

• If master sends more data bytes, the register address will be incremented by one after each acknowledge.

• Master generate stop condition to finish the write cycle.

From Slave to Master

S

Device Address

Register Address

0

A

A

Data

A

P

From Master to Slave

‘0’

Write

7 bits

8 bits

8 bits

S = Start

A = Acknowledge (SDA Low)

P = Stop