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ES9218PC Datasheet(PDF) 88 Page - ESS Technology,Inc

No. de pieza ES9218PC
Descripción Electrónicos  32-bit Stereo Low Power DAC with Headphone Amplifier, Analog Volume Control, and Output Switch
PDF  101 Pages
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Fabricante Electrónico  ESS [ESS Technology,Inc]
Página de inicio  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9218PC Datasheet(HTML) 88 Page - ESS Technology,Inc

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ES9218P Datasheet
December 6, 2018
CONFIDENTIAL ADVANCE INFORMATION 1.8
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801
88
Registers 66-69 (Read-Only): DPLL Number (0x42 - 0x45)
Bits
[31:0]
Mnemonic
dpll_num
Default
Bit
Mnemonic
Description
[31:0]
dpll_num
Contains the ratio between the CLK and the audio clock rate once the DPLL has acquired lock.
This value is latched on reading the LSB, so register 66 must be read first to acquire the latest DPLL
value and avoid data tearing. The value is latched on LSB because the DPLL number can change as
the I2C transactions are performed.
FSR =
(dpll_num ∗ CLK)
232



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