17

ICS950813

Advance Information

0708—10/10/02

The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch

low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next

rising edge.

PCI_STOP#

PCI_F[2:0] 33MHz

PCI[6:0] 33MHz

tsu

Assertion of PCI_STOP# Waveforms

PCI_STOP# - Assertion (transition from logic "1" to logic "0")

CPU_STOP# - Assertion (transition from logic "1" to logic "0")

Assertion of CPU_STOP# Waveforms

CPU_STOP# Functionality

#

P

O

T

S

_

U

P

CT

U

P

CC

U

P

C

1l

a

m

r

o

Nl

a

m

r

o

N

0t

l

u

M

*

f

e

r

it

a

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F

The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I

assertion of CPU_STOP# are to be stopped after their next transition. When the I

the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive

current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not

be driven . When the I

and CPU# outputs will not be driven.

CPU_STOP#

CPUCLKT

CPUCLKC