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CS47L85 Datasheet(PDF) 34 Page - Cirrus Logic

No. de pieza CS47L85
Descripción Electrónicos  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 34 Page - Cirrus Logic

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CS47L85
34
Rev 4.3
AUDIO INTERFACE TIMING
DIGITAL MICROPHONE (DMIC) INTERFACE TIMING
(left data)
(right data)
DMICDAT
(input)
VIL
VIH
tRH
tRSU
tLH
tLSU
VOL
DMICCLK
(output)
tCY
VOH
tr
tf
Figure 2 Digital Microphone Interface Timing
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Digital Microphone Interface Timing
DMICCLKn cycle time
tCY
160
163
1432
ns
DMICCLKn duty cycle
45
55
%
DMICCLKn rise/fall time (25pF load, 1.8V supply - see note)
tr, tf
5
30
ns
DMICDATn (Left) setup time to falling DMICCLK edge
tLSU
15
ns
DMICDATn (Left) hold time from falling DMICCLK edge
tLH
0
ns
DMICDATn (Right) setup time to rising DMICCLK edge
tRSU
15
ns
DMICDATn (Right) hold time from rising DMICCLK edge
tRH
0
ns
Notes:
DMICDATn and DMICCLKn are each referenced to a selectable supply, VSUP.
The applicable supply is selected using the INn_DMIC_SUP registers.
The voltage reference for the IN1, IN2 and IN3 digital microphone interfaces is selectable, using the INn_DMIC_SUP
registers - each interface may be referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or MICBIAS3 levels.
The voltage reference for the IN4, IN5 and IN6 digital microphone interfaces is DBVDD4.



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