APR347

Document number: DS41207 Rev. 5 - 2

7 of 9

www.diodes.com

December 2020

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APR347

Synchronous Rectification Principle Description (continued)

VDD

The VDD is the output voltage of the Pulse Linear Regulator (PLR) or the Low Dropout Regulator (LDO). It provides bias voltage for the controller.

A capacitor (typically 4.7μF) should be connected between the VDD pin and GND pin.

A Pulse Linear Regulator is integrated in the controller to provide voltage to the VDD pin of the APR347. With the PLR, the APR347 can operate at

a low voltage output condition, in which the system output voltage may drop to as low as 2V. The bias voltage will change from the PLR to the

LDO when the system output voltage is higher than 4.75V. In this case, the system output provides voltage to the APR347’s VDD through the

internal LDO.

Ordering Information

Package

Product Name

W6 : SOT26

7 : 7" Tape & Reel

APR347 X – X

Packing

Package

Temperature Range

Part Number

Marking ID

7”Tape and Reel

Quantity

Part Number Suffix

SOT26

-40°C to +85°C

APR347W6-7

CZ

3000/Tape and Reel

-7

Marking Information

1

2

3

6

4

CZ Y W X

XX : Identification Code

Y : Year 0~9

X : Internal Code

( Top View )

5

W : Week : A~Z : 1~26 week;

a~z : 27~52 week; z represents

52 and 53 week