STA8100GA datasheet(27/42 Pages) STMICROELECTRONICS

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DS13006 Rev 4

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STA8100GA

Electrical specifications

P_1dB

RF-IF-VGA input compression

Point

In band

RFA max VGA max

—-100

—

dBm

In band

RFA max VGA min

—-50

—

NFRF-IF

RF-IF-VGA noise figure(1)

VGA & RFA at max gain in

L1-L2-L5-L band

—5—

-1 dB high freq. corner IF filter

Set corner #1

—

MHz

Set corner #2

—

ATT

Aliasing frequency rejection

F = 51 MHz (corner #1)

—

F = 58 MHz (corner #2)

—

Fractional synthesizer – VCO

TCXO in

TCXO frequency

—

MHz

RDIV

Reference divider range

—

NDIV

Loop divider range

—

2047

—

Frac

PLL fractionality

—

bit

FLO

LO operating frequency

—

2300

—

3300

MHz

1. Specified by design.

Table 20. RF Electrical characteristics (Tj = 125 °C) (continued)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Table 21. Electrical characteristics of digital input and output buffers

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Input and output buffers

VIH_1V8

CMOS input high level

—

0.65

× V18_IO

—

0.3 + V18_IO

VIL_1V8

CMOS input high level

—

- 0.3

—

0.35

× V18_IO

VIH_3V3

CMOS input high level

—

2.0

—

0.3 + V33_IO

VIL_3V3

CMOS input high level

—

- 0.3

—

0.8

CIN

CMOS input capacitance

—

VOH

CMOS output high level

at max. IOH

VIO - 0.4

—

VOL

CMOS output low level

at max. IOL

—

0.4

IOL/IOH IO

ring1 and

PPS_OUT

Driving current to sustain

VOL/VOH

0—

IOL/IOH IO

ring2 but

PPS_OUT

Driving current to sustain

VOL/VOH

0—

tRISE(1)

CMOS output rise time

with CL = 15 pF, from 10

to 90 %; 3.3 V

2 mA max. current

drive

—3

—

4 mA max. current

drive

—2

—

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