L9654 datasheet(22/59 Pages) STMICROELECTRONICS

22 / 59 page

Functional description

L9654

22/59

DocID14218 Rev 3

4.8.4

Serial data input (MOSI, MOSI_A)

MOSI/MOSI_A input takes data from the master processor while chip select is asserted.

The MSB shall be the first bit of each word/byte received on MOSI/MOSI_A and the LSB

shall be the last bit of each word/byte received. This pin has TTL level compatible input

voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.

4.9

Deployment drivers

The on-chip deployment drivers are designed to deliver 1.2 A (mi.n) at 6.9 V VRES.

Deployment current is 1.2 A (min.) for 2 ms (min.). The high-side driver survives deployment

with 1.47 A, 35 V at VRES and SQL is shorted to ground for 2.5 ms. Minimum load

resistance is 1.7. At the end of a deployment, a deploy success flag is asserted via SPI.

Each VRES and GND connection are used to accommodate 4 loops that can be deployed

simultaneously.

Upon receiving a valid deployment condition, the respective SQH and SQL drivers are

turned on. SQH and SQL drivers are also turned on momentarily during a MOS diagnostic.

Otherwise, SQH and SQL are inactive under any normal, fault, or transient conditions. Upon

a successful deployment of the respective SQH and SQL drivers, a deploy command

success flag is asserted via SPI. Refer to "deployment sequence" Figure 10 for the valid

condition and the deploy success flag timing.

Figure 10. Deployment drivers diagram

The following power-up conditions are considered as normal operations . VRES input can

be connected to either a power supply output or an ignition voltage. VDD is connected to

5 V output of power supply. When VRES is connected to the power supply, VDD voltage

L9654 Datasheet(PDF) 22 Page - STMicroelectronics