L9374TRLF datasheet(47/80 Pages) STMICROELECTRONICS

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L9374LF

Circuit description

SPI: Parity failure

odd

on + off

– bit is set (latched)

– data are not used

Access SPI-register

SPI: SPICLK-failure

n <> 16

on + off

– bit is set (latched)

– data are not used

Access SPI-register

SPI: Data-failure

on + off

– bit is set (latched)

– data are not used (within a register)

Access SPI-register

CLKIN-failure

on + off

– bit is set (latched)

– all outputs switched off immediately

– all set points / current / duty cycle / durations are kept at

zero

– all counters are kept at zero

– all synchronization values are kept at zero (reset, sync,

STW)

– there is no influence at all status register

Access SPI-register

Sync-failure

STW_V_MIN < X <

STW_V_MAX

on + off – bit is set (latched)

Access SPI-register

Under voltage @ VS on + off

– all outputs switched off immediately

– all set points / current / duty cycle /durations are kept

zero

– all counters are kept at zero

– all synchronization values are kept at zero (reset, sync,

STW)

– all status register are kept at zero

– all input, outputs and data buffer are kept at default

Table 36. Fault diagnostic summary (continued)

Failure

Output

state

Effect

Reset behavior

L9374TRLF Datasheet(PDF) 47 Page - STMicroelectronics

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