Figure 8. Driver differential output rise and fall times and propagation delays

D

VL

A

B

VOD

50%

tPLH

tPHL

VI

VOD

10%

90%

tr

tf

0 V

≈ 2 V

≈ -2 V

VL

Figure 9. Driver enable and disable times with active high output and pull-down load

DE

VL

A

B

50%

tPZH

tPHZ

VI

VL

50 Ω

50%

VO

50%

0V

VO

≈ 0V

VOH

90%

0V5

VI

Figure 10. Driver enable and disable times with active low output and pull-up load

DE

VL

A

B

RL = 110 Ω ± 1%

CL = 50 pF ± 20%

50%

tPZL

tPLZ

VI

VO

≈ VL

50 Ω

VI

50%

VO

50%

10%

VOL

0 V

VL

≈ 3 V

STR485E

Test circuits and typical characteristics

DS13051 - Rev 3

page 12/26