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UPSD3312D-40U6 Datasheet(PDF) 64 Page - STMicroelectronics |
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UPSD3312D-40U6 Datasheet(HTML) 64 Page - STMicroelectronics |
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64 / 231 page  uPSD33xx 64/231 Table 36. Number of MCU_CLK Periods Required to Optimize Bus Transfer Rate Note: 1. VDD of the PSD Module 2. “Turbo mode PSD” means that the PSD Module is in the faster, Turbo mode (default condition). A PSD Module in Non-Turbo mode is slower, but consumes less current. See PSD Module section, titled “PLD Non-Turbo Mode” for details. MCU Clock Frequency, MCU_CLK (fMCU) CW[1:0] Clk Periods RDW[1:0] Clk Periods WRW[1:0] Clk Periods 3.3V(1) 5V(1) 3.3V(1) 5V(1) 3.3V(1) 5V(1) 40MHz, Turbo mode PSD(2) 545 454 40MHz, Non-Turbo mode PSD 6 5 6 5 6 5 36MHz, Turbo mode PSD 545 454 36MHz, Non-Turbo mode PSD 6 4 6 4 6 4 32MHz, Turbo mode PSD 545 454 32MHz, Non-Turbo mode PSD 5 4 5 4 5 4 28MHz, Turbo mode PSD 434 444 28MHz, Non-Turbo mode PSD 5 4 5 4 5 4 24MHz, Turbo mode PSD 434 444 24MHz, Non-Turbo mode PSD 4 3 4 4 4 4 20MHz and below, Turbo mode PSD 334 444 20MHz and below, Non-Turbo mode PSD 3 3 4 4 4 4 |
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