ILPS22QSTR datasheet(26/57 Pages) STMICROELECTRONICS

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7.2.1

I²C operation

The transaction on the bus is started through a start (ST) signal. A start condition is defined as a high to low

transition on the data line while the SCL line is held high. After the master has transmitted this, the bus is

considered busy. The next data byte transmitted after the start condition contains the address of the slave in the

first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the

slave. When an address is sent, each device in the system compares the first seven bits after a start condition

with its address. If they match, the device considers itself addressed by the master.

The 7-bit slave address (SAD) associated to the ILPS22QS is 1011100b = 5Ch.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge

pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the

acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each

byte of data received.

The I²C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered

to. After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK),

an 8-bit subaddress is transmitted (SUB). The IF_ADD_INC bit in CTRL_REG2 (11h) enables subaddress auto

increment (IF_ADD_INC is 1 by default), so if IF_ADD_INC = 1 the SUB (subaddress) is automatically increased

to allow multiple data read/write.

The slave address is completed with a read/write bit. If the bit is 1 (read), a repeated start (SR) condition must

be issued after the two subaddress bytes; if the bit is 0 (write) the master transmits to the slave with direction

unchanged. The following table explains how the SAD+read/write bit pattern is composed, listing all the possible

configurations.

Table 13. SAD+read/write patterns

Command

SAD[6:0]

R/W

SAD+R/W

Read

1011100

10111001 (B9h)

Write

1011100

10111000 (B8h)

Table 14. Transfer when master is writing one byte to slave

Master

SAD+ W

SUB

DATA

Slave

SAK

Table 15. Transfer when master is writing multiple bytes to slave

Master

SAD+ W

SUB

DATA

Slave

SAK

Table 16. Transfer when master is receiving (reading) one byte of data from slave

Master

SAD+ W

SUB

SAD+ R

NMAK

Slave

SAK

DATA

Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave

Master

SAD+W

SUB

SAD+R

MAK

NMAK

Slave

SAK

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred

per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a slave receiver does not

acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function),

the data line must be kept high by the slave. The master can then abort the transfer. A low to high transition on

the SDA line while the SCL line is high is defined as a stop condition. Each data transfer must be terminated by

the generation of a stop (SP) condition.

In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge.

ILPS22QS

I²C serial interface (CS = high)

DS13431 - Rev 3

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