D301 datasheet(335/416 Pages) MICROCHIP

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DS30010118D-page 335

PIC24FJ256GA705 FAMILY

FWDT CONFIGURATION REGISTER

U-1

—

bit 23

bit 16

U-1

R/PO-1

U-1

R/PO-1

U-1

R/PO-1

—

WDTCLK1

WDTCLK0

—

WDTCMX

—

WDTWIN1

WDTWIN0

bit 15

bit 8

R/PO-1

WINDIS

FWDTEN1

FWDTEN0

FWPSA

WDTPS3

WDTPS2

WDTPS1

WDTPS0

bit 7

bit 0

Legend:

PO = Program Once bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-15

Unimplemented: Read as ‘1’

bit 14-13

WDTCLK<1:0>: Watchdog Timer Clock Select bits (when WDTCMX = 1)

11 = Always uses LPRC

10 = Uses FRC when WINDIS = 0, system clock is not LPRC and device is not in Sleep; otherwise,

uses LPRC

01 = Always uses SOSC

00 = Uses peripheral clock when system clock is not LPRC and device is not in Sleep; otherwise, uses

LPRC

bit 12

Unimplemented: Read as ‘1’

bit 11

WDTCMX: WDT Clock MUX Control bit

1 = Enables WDT clock MUX, WDT clock is selected by WDTCLK<1:0>

0 = WDT clock is LPRC

bit 10

Unimplemented: Read as ‘1’

bit 9-8

WDTWIN<1:0>: Watchdog Timer Window Width bits

11 = WDT window is 25% of the WDT period

10 = WDT window is 37.5% of the WDT period

01 = WDT window is 50% of the WDT period

00 = WDT window is 75% of the WDT period

bit 7

WINDIS: Windowed Watchdog Timer Disable bit

1 = Windowed WDT is disabled

0 = Windowed WDT is enabled

bit 6-5

FWDTEN<1:0>: Watchdog Timer Enable bits

11 = WDT is enabled

10 = WDT is disabled (control is placed on the SWDTEN bit)

01 = WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled

00 = WDT and SWDTEN are disabled

bit 4

FWPSA: Watchdog Timer Prescaler bit

1 = WDT prescaler ratio of 1:128

0 = WDT prescaler ratio of 1:32

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