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N2L Datasheet(PDF) 75 Page - Renesas Technology Corp |
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N2L Datasheet(HTML) 75 Page - Renesas Technology Corp |
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75 / 127 page ![]() Corresponding bit in the SPOER register MTU PWM output pins Outputs disabled tPOEDS Figure 2.45 Output disable time for POE in response to the register setting MTU PWM output pins Oscillation stop detection signal (internal signal) Main clock Outputs disabled tPOEDOS Figure 2.46 Output disable time for POE in response to the oscillation stop detection 2.5.5.5 GPT Timing Table 2.29 GPT timing Parameter Symbol Min. Max. Unit*1 Reference figure GPT Input capture input pulse width Single-edge setting tGTICW 2.5 — tPHcyc Figure 2.47 Both-edge setting 3.5 — External trigger input pulse width Single-edge setting tGTEW 2.5 — tPHcyc Figure 2.48 Both-edge setting 3.5 — Note 1. tPHcyc: PCLKH cycle (LLPP channels), PCLKM cycle (Other channels) PCLKH, PCLKM tGTICW Input capture input Figure 2.47 GPT input capture input timing PCLKH tGTEW External trigger Figure 2.48 GPT external trigger input timing RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 75 of 127 |
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