WM8940CGEFLSLASHV datasheet(53/88 Pages) CIRRUS

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WM8940

Rev 4.4

LEFT CHANNEL

RIGHT CHANNEL

LRC

BCLK

DACDAT /

ADCDAT

n-2 n-1

LSB

MSB

n-2 n-1

1 BCLK

Input Word Length (WL)

1/fs

falling edge can occur anywhere in this area

1 BCLK

Figure 29 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1)

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below.

FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with

BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at

the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Audio interface

control

LOUTR

LOUTR control

0=normal

1=Input mono channel data output on

both left and right channels

BCP

BCLK polarity

0=normal

1=inverted

FRAMEP

Frame clock polarity (for RJ, LJ and I2S

formats)

0=normal

1=inverted

DSP Mode control

1 = Configures interface so that MSB is

available on 1st BCLK rising edge after

FRAME rising edge

0 = Configures interface so that MSB is

available on 2nd BCLK rising edge after

FRAME rising edge

6:5

Word length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see note)

4:3

FMT

Audio interface Data Format Select:

00=Right Justified

01=Left Justified

10=I2S format

11= DSP/PCM mode

WM8940CGEFL/V Datasheet(PDF) 53 Page - Cirrus Logic

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