VSC8021 datasheet(3/17 Pages) VITESSE

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VITESSE

SEMICONDUCTOR CORPORATION

G52028-0, Rev 4.1

Page 3

05/25/01

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Data Sheet

VSC8021/VSC8022

8-Bit MUX/DEMUX Chipset

2.5Gb/s SONET-Compatible

VSC8022

The VSC8022 contains both a 1:8 demultiplexer and SONET frame recovery circuitry. The 1:8 demultiplexer

accepts a serial data input (

DI, DIN) at rates up to 2.5Gb/s and converts it into 8 parallel differential ECL data outputs

(

D1-D8, D1N-D8N) at rates up to 312.5Mb/s. Valid parallel data outputs are indicated by the divide by 8 differential

clock outputs

BYCKO, BYCKON.

The VSC8022 also contains a SONET frame recovery circuit. The frame recovery circuits are enabled by a fall-

ing edge on the

OOFN ECL input when the FDIS input is low. Once enabled, the frame recovery circuit starts look-

ing for the SONET framing sequence. Once the frame is detected, the word boundary is realigned, a confirmation

signal is sent off-chip through the

FP ECL output and the frame recovery circuits are disabled. While the frame

aligner is hunting for the frame,

BYCKO, BYCKON and parallel data are invalid.

Figure 2: VSC8022 Block Diagram

Frame recovery circuits are disabled by frame detection (resulting in FP) or by a falling edge on the OOFN

input while FDIS is high.

Parallel

Data Outputs

Serial Data In

1:8

Demultiplexer

Timing

Generator

High Speed

Clock Inputs

— Frame Detection Signal

CLKI

CLKIN

DIN

D1N

Byte Clock Out

BYCKO

BYCKON

D8N

SONET

Frame

Detection &

Recovery

FDIS

OOFN

Frame Recovery Disable —

Frame Recovery Clock —

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