STM8L051F3 datasheet(77/96 Pages) STMICROELECTRONICS

77 / 96 page

DS9178 Rev 4

77/96

STM8L051F3

Electrical parameters

I2C - Inter IC control interface

Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified.

The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C

communication protocol described in the following table with the restriction mentioned

below:

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SDA and SCL).

Note:

For speeds around 200 kHz, the achieved speed can have a

± 5% tolerance

For other speed ranges, the achieved speed can have a

± 2% tolerance

The above variations depend on the accuracy of the external components used.

Table 41. I2C characteristics

Symbol

Parameter

Standard mode

I2C

Fast mode I2C(1)

Unit

Min(2)

Max (2)

Min (2)

Max (2)

tw(SCLL)

SCL clock low time

4.7

1.3

μs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

900

tr(SDA)

tr(SCL)

SDA and SCL rise time

1000

300

tf(SDA)

tf(SCL)

SDA and SCL fall time

300

th(STA)

START condition hold time

4.0

0.6

μs

tsu(STA)

Repeated START condition setup

time

4.7

0.6

tsu(STO)

STOP condition setup time

4.0

0.6

μs

tw(STO:STA)

STOP to START condition time (bus

free)

4.7

1.3

μs

Capacitive load for each bus line

400

1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).

2. Data based on standard I2C protocol requirement, not tested in production.

STM8L051F3 Datasheet(PDF) 77 Page - STMicroelectronics

STM8L051F3 Datasheet(HTML) 77 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Descarga

Enlace URL