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STM32L011D4P7 Datasheet(PDF) 78 Page - STMicroelectronics

No. de pieza STM32L011D4P7
Descripción Electrónicos  Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, up to 16KB Flash, 2KB SRAM, 512B EEPROM, ADC
PDF  119 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L011D4P7 Datasheet(HTML) 78 Page - STMicroelectronics

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Electrical characteristics
STM32L011x3/4
78/119
DocID027973 Rev 5
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 25 and
Table 52, respectively.
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 18.
Table 52. I/O AC characteristics(1)(2)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Parameter
Conditions
Min
Max(3) Unit
00
fmax(IO)out Maximum frequency(4)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
100
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
320
01
fmax(IO)out Maximum frequency(4)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
0.6
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
65
10
Fmax(IO)out Maximum frequency(4)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
13
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
28
11
Fmax(IO)out Maximum frequency(4)
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
35
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
10
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
6
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
17
-tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-8
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO
Port configuration register.
2. BOOT0/PB9 maximum input frequency is 10 kHz (1.65 V < VDD < 2.7 V) and 5 MHz (2.7 V < VDD <3.6 V).
3. Guaranteed by design. Not tested in production.
4. The maximum frequency is defined in Figure 25.



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