LTC4232 datasheet(11/18 Pages) AD

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LT4200

Rev. 0

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APPLICATIONS INFORMATION

This gate slope is designed to charge up a 1000µF capaci-

tor to 12V in 34ms, with an inrush current of 350mA. This

allows the inrush current to stay under the folded back

current limit threshold (6.8A) for capacitors less than

8mF. The average power dissipation of 12V at 350mA for

34ms amounts to 0.387W√s, which is safely below the

LT4200 P√t spec of 7.5W√s.

The default configuration results in an inrush current

that stays under the folded back current limit thresh-

old (6.8A) for charging capacitors less than 7667µF. If

the load capacitor, CL, is greater than 7667μF or a reduced

inrush current is desired, an RC network can be added to

the GATE pin. This is illustrated in Figure 1. With the RC

network the inrush current is defined by Equation 2. The

resistor should be 100k. A 3.3nF, CCOMP, is necessary to

compensate the current limit.

IINRUSH =

CGATE

•24µA

(2)

When the GATE voltage reaches the MOSFET threshold

voltage, the switch begins to turn on and the OUT volt-

age follows the GATE voltage as it increases. Once OUT

reaches VDD, the GATE will ramp up until clamped by the

12V Zener between GATE and OUT.

As the OUT voltage rises, so will the FB pin which is moni-

toring it. Once the FB pin crosses its 1.235V threshold

and the GATE to OUT voltage exceeds 4.2V, the PG pin

will cease to pull low and indicate that the power is good.

Parasitic MOSFET Oscillation

When the N-channel MOSFET ramps up the output dur-

ing power-up it operates as a source follower. The source

follower configuration may self-oscillate in the range of

25kHz to 300kHz when the load capacitance is less than

10µF, especially if the wiring inductance from the supply

to VDD pin is greater than 3µH. The possibility of oscil-

lations will increase as the load current (during power-

up) increases. There are two ways to prevent this type of

oscillation. The simplest way is to avoid load capacitances

below 10µF. For wiring inductances larger than 20µH,

the minimum load capacitance may extend to 100µF.

A second choice is to connect an external gate capacitor

CP > 1.5nF as shown in Figure 3.

4200 F03

LT4200

GATE

2.2nF

OPTIONAL

RC TO LOWER

INRUSH CURRENT

Figure 3. Compensation for Small CLOAD

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated when the UV pin goes below

its 1.235V threshold. Additionally, several fault conditions

will turn off the switch. These include an input overvolt-

age (OV pin), overcurrent circuit breaker (SENSE+ pin) or

overtemperature. Normally, the switch is turned off with a

250µA current pulling down the GATE pin to ground. With

the switch turned off, the OUT voltage drops which pulls

the FB pin below its threshold. The PG then pulls low to

indicate output power is no longer good.

If VDD drops below 2.65V for greater than 5µs or INTVCC

drops below 2.5V for greater than 1µs, a fast shut down

of the switch is initiated. The GATE is pulled down with a

140mA current to the OUT pin.

Overcurrent Fault

The LT4200 features an adjustable current limit with

foldback that protects against short circuits and exces-

sive load current. To protect against excessive power

dissipation in the switch during active current limit, the

available current is reduced as a function of the output

voltage sensed by the FB pin. A graph in the Typical

Performance Characteristics curves shows the current

limit threshold foldback.

An overcurrent fault occurs when the current limit cir-

cuitry has been engaged for longer than the timeout

delay set by the TIMER. Current limiting begins when

the MOSFET current reaches 6.8A to 57A (depending on

the foldback). The GATE pin is then brought down with a

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