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AD4116BCPZ Datasheet(PDF) 19 Page - Analog Devices

No. de pieza AD4116BCPZ
Descripción Electrónicos  Single Supply, 24-Bit, Sigma-Delta ADC with 짹10 V, 10 M廓 Inputs and Buffered Low Level Inputs
PDF  59 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD4116BCPZ Datasheet(HTML) 19 Page - Analog Devices

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Data Sheet
AD4116
Rev. 0 | Page 19 of 59
Default ODR (SPS);
SING_CYC = 0 and
Single Channel Enabled
ODR (SPS per Channel);
SING_CYC = 1 or
Multiple Channels Enabled
Settling
Time1
Notch
Frequency
(Hz)
Noise
(μV rms)2
Effective
Resolution
(Bits)
Noise
(μV p-p)
Peak-to-Peak
Resolution
(Bits)
10
3.33
300.00 ms
10.00
8.25
21.20
42.91
18.80
5
1.67
600.00 ms
5.00
8.25
21.20
41.72
18.85
2.5
0.83
1.20 sec
2.50
8.13
21.23
41.72
18.88
1.25
0.42
2.4 sec
1.25
6.68
21.51
33.38
19.20
1 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 Based on 1000 samples for data rates ≥ 59.98 SPS per channel, and based on 100 samples for data rates ≤ 50 SPS per channel.
Table 9. ±VREF Low-level Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter
Default ODR (SPS);
SING_CYC = 0 and
Single Channel Enabled
ODR (SPS per Channel);
SING_CYC = 1 or Multiple
Channels Enabled
Settling
Time1
Notch
Frequency
(Hz)
Noise
(μV rms)2
Effective
Resolution
(Bits)
Noise
(μV p-p)
Peak-to-Peak
Resolution
(Bits)
62,500
12,422.36
80.5 μs
62,500
9.6
18.99
63.36
16.27
31,250
10,362.69
96.5 μs
31,250
8.3
19.20
54.78
16.48
15,625
7,782.1
128.5 μs
15,625
6.3
19.60
41.58
16.88
10,416.7
6,230.53
160.5 μs
10,416.7
6.1
19.79
36.3
17.07
5,194.8
5,194.8
192.5 μs
7,812.5
4.9
19.96
32.34
17.24
2,496.9
2,496.9
400.5 μs
2,976.19
3.2
20.58
21.12
17.85
1007.6
1007.6
992.50 μs
1077.59
1.95
21.29
12.87
18.57
499.9
499.9
2.00 ms
516.53
1.3
21.87
8.58
19.15
390.6
390.6
2.56 ms
400.64
1.2
21.99
7.92
19.27
200.3
200.3
4.99 ms
202.92
0.85
22.49
5.61
19.77
100.0
100.0
10.00 ms
100.6
0.6
22.99
3.96
20.27
59.75
59.75
16.74 ms
59.98
0.45
23.41
2.97
20.68
49.84
49.84
20.06 ms
50
0.4
23.58
2.64
20.85
20.00
20.00
50.00 ms
20.03
0.26
24
1.716
21.47
16.65
16.65
60.06 ms
16.67
0.23
24
1.518
21.65
10.00
10.00
100.00 ms
10.01
0.18
24
1.188
22.00
5.00
5.00
200.00 ms
5
0.13
24
0.858
22.47
2.50
2.50
400.00 ms
2.5
0.09
24
0.594
23.00
1.25
1.25
800.00 ms
1.25
0.07
24
0.462
23.37
1 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 Based on 1000 samples for data rates ≥ 59.98 SPS per channel, and based on 100 samples for data rates ≤ 50 SPS per channel.
Table 10. ±VREF Low Level Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter
Default ODR (SPS);
SING_CYC = 0 and
Single Channel Enabled
ODR (SPS per Channel);
SING_CYC = 1 or Multiple
Channels Enabled
Settling
Time1
Notch
Frequency
(Hz)
Noise
(μV rms)2
Effective
Resolution
(Bits)
Noise
(μV p-p)
Peak-to-Peak
Resolution
(Bits)
62,500
20,618.56
48.5 μs
62,500
105
15.54
693
12.82
31,250
10,362.69
96.5 μs
31,250
14
18.45
92.4
15.72
15,625
5,194.81
192.5 μs
15,625
5.8
19.72
38.28
16.99
10,416.7
3,466.2
288.5μs
10,416.7
4.7
20.02
31.02
17.30
5,208.3
1,734.61
576.5 μs
5,208.3
3.2
20.58
21.12
17.85
2,500
832.99
1.20 ms
2,500
1.95
21.29
12.87
18.57
1008.1
335.97
2.98 ms
1008.1
1.45
21.72
9.57
18.99
500
166.65
6.00 ms
500
0.98
22.28
6.468
19.56
400.64
133.54
7.49 ms
400.64
0.9
22.41
5.94
19.68
200.32
66.77
14.98 ms
200.32
0.64
22.90
4.224
20.17
100.0
33.3
30.00 ms
100.0
0.45
23.41
2.97
20.68
59.98
19.99
50.02 ms
59.98
0.33
23.85
2.178
21.13



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