EDB8164B4PR-1DATF-R datasheet(113/152 Pages) MICRON

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2. For CK_t and CK_c, use VIH/VIL(AC) of CA and VREFCA; for DQS_t and DQS_c, use VIH/VIL(AC)

of DQ and VREFDQ. If a reduced AC HIGH or AC LOW is used for a signal group, the re-

duced voltage level also applies.

3. Used to define a differential signal slew rate. For CK_t - CK_c use VIH/VIL(dc) of CA and

VREFCA; for DQS_t - DQS_c, use VIH/VIL(dc) of DQs and VREFDQ; if a reduced dc-high or

dc-low level is used for a signal group,then the reduced level applies also here.

Table 72: CK_t/CK_c and DQS_t/DQS_c Time Requirements Before Ringback (tDVAC)

Slew Rate (V/ns)

tDVAC (ps) at VIH/VILdiff(AC) = 440mV

tDVAC (ps) at VIH/VILdiff(AC) = 600mV

Min

> 4.0

175

4.0

170

3.0

167

2.0

163

1.8

162

1.6

161

1.4

159

1.2

155

1.0

150

< 1.0

150

Single-Ended Requirements for Differential Signals

Each individual component of a differential signal (CK_t, CK_c, DQS_t, and DQS_c)

must also comply with certain requirements for single-ended signals.

CK_t and CK_c must meet VSEH(AC)min/VSEL(AC)max in every half cycle. DQS_t, DQS_c

must meet VSEH(AC)min/VSEL(AC)max in every half cycle preceding and following a valid

transition.

The applicable AC levels for CA and DQ differ by speed bin.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

AC and DC Logic Input Measurement Levels for Differential

Signals

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

113

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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