EDB8164B4PR-1DATF-R datasheet(109/152 Pages) MICRON

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The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and

VIL(DC) are dependent on VREF.

VREF DC variations affect the absolute voltage a signal must reach to achieve a valid

HIGH or LOW, as well as the time from which setup and hold times are measured. When

VREF is outside the specified levels, devices will function correctly with appropriate tim-

ing deratings as long as:

•VREF is maintained between 0.44 x VDDQ (or VDD2) and 0.56 x VDDQ (or VDD2), and

• the controller achieves the required single-ended AC and DC input levels from instan-

taneous VREF (see the Single-Ended AC and DC Input Levels for CA and CS_n Inputs

table).

System timing and voltage budgets must account for VREF deviations outside this range.

The setup/hold specification and derating values must include time and voltage associ-

ated with VREF AC noise. Timing and voltage effects due to AC noise on VREF up to the

specified limit (±1% VDD) are included in LPDDR2 timings and their associated derat-

ings.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

AC and DC Logic Input Measurement Levels for Single-Ended

Signals

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

109

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDB8164B4PR-1DATF-R Datasheet(PDF) 109 Page - Micron Technology