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SH7041A Datasheet(PDF) 187 Page - Renesas Technology Corp

No. de pieza SH7041A
Descripción Electrónicos  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
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SH7041A Datasheet(HTML) 187 Page - Renesas Technology Corp

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149
Register
information
start address
Memory space
Memory space
Memory space
Register
information
Normal mode
Repeat mode
Block transfer mode
DTMR
DTCRA
DTSAR
DTDAR
DTMR
DTCRA
DTSAR
DTDAR
DTIAR
DTMR
DTCRA
DTSAR
DTDAR
DTCRB
Figure 8.5 DTC Register Information Placement in Memory Space
8.3.5
Normal Mode
Performs the transfer of one byte, one word, or one longword for each activation. The total
transfer count is 1 to 65536. An interrupt request is generated to the CPU when the transfer with
DTCRA = 1 ends. Transfers of a number of bytes specified by the SCI are possible.
Table 8.3 shows the register functions for normal mode.
Table 8.3
Normal Mode Register Functions
Values Written Back upon a
Transfer Information Write
Register
Function
When DTCRA
is other than 1
When DTCRA is 1
DTMR
Operation mode
control
DTMR
DTMR
DTCRA
Transfer count
DTCRA – 1
DTCRA – 1 (= H'0000)
DTSAR
Transfer source
address
Increment/decrement/
fixed
Increment/decrement/
fixed
DTDAR
Transfer destination
address
Increment/decrement/
fixed
Increment/decrement/
fixed
8.3.6
Repeat Mode
Performs the transfer of one byte, one word, or one longword for each activation. Either the
transfer source or transfer destination is designated as the repeat area.



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