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SH7041A Datasheet(PDF) 435 Page - Renesas Technology Corp

No. de pieza SH7041A
Descripción Electrónicos  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
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SH7041A Datasheet(HTML) 435 Page - Renesas Technology Corp

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397
12.7.9
Contention between TGR Write and Compare Match
If a compare-match occurs in the T
2 state of the TGR write cycle, data is written to the TGR and a
compare-match signal is issued (figure 12.84).
TGR
Compare
match signal
TCNT
Address
Write signal
φ
T1
T2
TGR write cycle
TGR address
N
N + 1
M
N
TGR write data
Figure 12.84 TGR Write and Compare Match Contention
12.7.10
TCNT2 Write and Overflow/Underflow Contention in Cascade Connection
With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs
during TCNT1 count (during a TCNT2 overflow/underflow) in the T
2 state of the TCNT2 write
cycle, the write to TCNT2 is conducted, and the TCNT1 count signal is prohibited. At this point, if
there is match with TGR1A or TGR1B and the TCNT1 value, a compare signal is issued. The
timing is shown in figure 12.85.
For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT
clearing.



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