Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

Preview PDF HTML

SH7041A Datasheet(PDF) 345 Page - Renesas Technology Corp

No. de pieza SH7041A
Descripción Electrónicos  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 345 Page - Renesas Technology Corp

Back Button SH7041A Datasheet HTML 341Page - Renesas Technology Corp SH7041A Datasheet HTML 342Page - Renesas Technology Corp SH7041A Datasheet HTML 343Page - Renesas Technology Corp SH7041A Datasheet HTML 344Page - Renesas Technology Corp SH7041A Datasheet HTML 345Page - Renesas Technology Corp SH7041A Datasheet HTML 346Page - Renesas Technology Corp SH7041A Datasheet HTML 347Page - Renesas Technology Corp SH7041A Datasheet HTML 348Page - Renesas Technology Corp SH7041A Datasheet HTML 349Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 345 / 923 page
background image
307
Channels 1, 2: TIER1, TIER2:
Bit:
7
6
5
4
3
2
1
0
TTGE
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
Initial value:
0
1
0
0
0
0
0
0
R/W:
R/W
R
R/W
R/W
R
R
R/W
R/W
Channels 3, 4: TIER3, TIER4:
Bit:
7
6
5
4
3
2
1
0
TTGE
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
Initial value:
0
1
0
0
0
0
0
0
R/W:
R/W
R
R
R/W
R/W
R/W
R/W
R/W
• Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an
A/D conversion start request by a TGRA register input capture/compare-match.
Bit 7: TTGE
Description
0
Disable A/D conversion start requests (initial value)
1
Enable A/D conversion start request generation
• Bit 6—Reserved: This bit is reserved. It always reads as 0, and cannot be modified.
• Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests when the
underflow flag (TCFU) of the channel 1, 2 timer status register (TSR) is set to 1.
This bit is reserved for channels 0, 3, and 4. It always reads as 0. The write value should
always be 1.
Bit 5: TCIEU
Description
0
Disable UDF interrupt requests (TCIU) (initial value)
1
Enable UDF interrupt requests (TCIU)
• Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the
overflow flag TCFV of the timer status register (TSR) is set to 1.
Bit 4: TCIEVDescription
0
Disable TCFV interrupt requests (TCIV) (initial value)
1
Enable TCFV interrupt requests (TCIV)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Descarga

Go To PDF Page


Enlace URL



¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Enlace a la hoja de datos    |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com