IMX7ULPIECB2 datasheet(22/112 Pages) NXP

22 / 112 page

2.1 Introduction

This section details the clock sources, distribution and management within the i.MX

7ULP. These functions are under joint control of the System Clock Generation (SCG)

modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)

blocks.

NOTE

References in this chapter to “Core 0” or “Processor A”

correspond to the Cortex M4 core. References in this chapter

to “Core 1” or “Processor B” correspond to the Cortex A7

core.

The clocking scheme provides clear separation between M4 domain and A7 domain.

Except for a few clock sources shared between two domains, such as the System

Oscillator clock, the Slow IRC (SIRC), and the Fast IRC clock (FIRC), clock sources

and clock management are separated and contained within each domain.

M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.

A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.

2.2 Clock distribution

The SCG modules generate and distribute clocks on the device. SCG functions include:

• clock reference selection

• generation of clock used to derive processor, system, peripheral bus and external

memory interface clocks

• source selection for peripheral clocks

• control of power-saving clock-gating mode

PCC modules control clock selection, optional division and clock gating mode for

peripherals.

NOTE

• To bypass system oscillator and directly apply clock from

pin, SCG_SOSCCFG[EREFS] should be set to 0. The

direct clock should be applied on the EXTAL pin.

• For using oscillator reference,

SCG_SOSCCSR[SOSCEN] and

SCG_SOSCCFG[EREFS] should both be set to 1.

Clocking

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

IMX7ULPIECB2 Datasheet(PDF) 22 Page - NXP Semiconductors