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ICS853111AY Datasheet(PDF) 9 Page - Integrated Circuit Systems

No. de pieza ICS853111AY
Descripción Electrónicos  LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PDF  18 Pages
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Fabricante Electrónico  ICST [Integrated Circuit Systems]
Página de inicio  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS853111AY Datasheet(HTML) 9 Page - Integrated Circuit Systems

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853111AY
www.icst.com/products/hiperclocks.html
REV. B MAY 14, 2004
9
Integrated
Circuit
Systems, Inc.
ICS853111A
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FIGURE 3B. LVPECL OUTPUT TERMINATION
FIGURE 3A. LVPECL OUTPUT TERMINATION
TERMINATION FOR 3.3V LVPECL OUTPUTS



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