DS2792 Programmable Fuel Gauge with UART Interface

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I/O PORTS

The DS2792 includes a simple input/output (I/O) data port. From a software perspective, the port appears as a

group of special-function registers within module M0. The simple I/O port defined for this product is described

below:

The port is accessed through five peripheral registers (PO, PI, PAF, PPU, and EIC) addressed either by byte or by

individual bit locations. The I/O port is designed to provide programming flexibility for the application. All individual

I/O pins are independently configured; and can be defined as an input, output, or alternate function. Table 7

summarizes the functionality of the I/O pins.

Table 7. I/O Port Pins

FUNCTIONS

CHARACTERISTICS

Primary

Alternate

TAP

*

Bidirectional

Weak Passive

Pulldown

Weak Active Pullup Strong Active Pullup

P0.0

INT0

TDI

*

Configurable, [In]

—

Configurable, [Off]

—

P0.1

INT1

TMS

*

Configurable, [In]

—

Configurable, [Off]

—

P0.2

RST*

—

Configurable, [In]

—

Configurable, [Off]

—

P0.3

—

TCK

*

Configurable, [In]

—

Configurable, [Off]

—

P0.4

—

TDO*

Configurable, [In]

—

—

Configurable, [Off]

P0.5

—

—

Configurable, [In]

—

—

Configurable, [Off]

TXD

—

—

Output

Configurable, [On]

Configurable, [Off]

—

RXD

—

—

Input

Configurable, [On]

Configurable, [Off]

—

Note: Reset values are denoted with an * and by [ ].

PI Register: The PI register is a read-only input of the I/O pins. When the register is read, the logic level of each

pin is reported in the corresponding bit locations. Reading a logic-low or high on a pin does not change the output

drive on that pin.

PO Register: The PO register controls the output state of the I/O pins. Data written to this register determines the

pin output drive. When a bit is written to a “0” (cleared), the n-channel output drive transistor is enabled, and the

pullup is disabled. When bit is written to a “1” (set), the n-channel output drive transistor is disabled, and the pullup

enabled (if so configured). The PO bits are set asynchronously during power-on reset to disable the N-channel

output drive. PO bits are not altered in SLEEP mode, however drive to the n-channel is disabled.

PPU Register: The PPU register contains independent bits that define each pin as high impedance or pulled up

when its n-channel output drive transistor is disabled. P0.0 through P0.3 have weak pullups, P0.4 and P0.5 have

strong pullups. When the output is disabled and the PPU bit is cleared, the pin is high impedance. When the output

is disabled and the PPU bit is set, the pin’s weak or strong pullup is enabled. When the PPU bit is set and the

device enters STOP mode, the weak pullup remains enabled.

PAF Register: The PAF register enables or disables the alternate functions of P0.0–P0.2. When a pin’s PAF bit is

cleared, the pin is controlled by the PI, PO, PPU, and EIC registers. When the PAF bit is set, the pin operates in it’s

alternate function mode. The

RST function of P0.2 can be disabled by writing the RSTD bit to 1.

EIC Register: The lower six bits of the EIC register are the port interrupt control bits. The port interrupt control bits

are used to enable and configure detection of external interrupts. Interrupt enable bits, PIE.0 and PIE.1, enable

detection of an interrupt on pins P0.0 and P0.1, respectively. Interrupt type bits, PIT.0 and PIT.1, define the type

(level or edge) of interrupt on pins P0.0 and P0.1, respectively. Interrupt polarity bits, PIP.0 and PIP.1, determine

the interrupt polarity on pins P0.0 and P0.1, respectively.