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ICS85322AMIT Datasheet(PDF) 6 Page - Integrated Circuit Systems

No. de pieza ICS85322AMIT
Descripción Electrónicos  DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
PDF  13 Pages
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Fabricante Electrónico  ICST [Integrated Circuit Systems]
Página de inicio  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS85322AMIT Datasheet(HTML) 6 Page - Integrated Circuit Systems

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85322AMI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 7, 2003
6
Integrated
Circuit
Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
APPLICATION INFORMATION
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
(V
OH + VOL / VCC – 2) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion.
Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 1B. LVPECL OUTPUT TERMINATION
FIGURE 1A. LVPECL OUTPUT TERMINATION



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