ICS5314AI11L datasheet(10/18 Pages) ICST

10 / 18 page

85314AGI-11

www.icst.com/products/hiperclocks.html

REV. C MAY 24, 2005

Integrated

Circuit

Systems, Inc.

ICS85314I-11

LOW SKEW, 1-TO-5

DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER

The clock layout topology shown below is a typical termi-

nation for LVPECL outputs. The two different layouts men-

tioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

CC - 2V

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

o = 50Ω

FOUT

FIN

FIGURE 4B. LVPECL OUTPUT TERMINATION

FIGURE 4A. LVPECL OUTPUT TERMINATION

TERMINATION FOR 3.3V LVPECL OUTPUTS

designed to drive 50

Ω transmission lines. Matched imped-

ance techniques should be used to maximize operating

frequency and minimize signal distortion. Figures 4A and

4B show two different layouts which are recommended only

as guidelines. Other suitable clock layouts may exist and it

would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock

component process variations.

ICS5314AI11L Datasheet(PDF) 10 Page - Integrated Circuit Systems