ICS601-21 datasheet(1/6 Pages) ICST

No. de pieza	ICS601-21

Descripción Electrónicos	LOW PHASE NOISE CLOCK MULTIPLIER

PDF	6 Pages

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Fabricante Electrónico	ICST [Integrated Circuit Systems]

Página de inicio	http://www.icst.com

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ICS601-21

MDS 601-21 H

1

Revision 040204

Integr ated Circuit Sy stems l 5 25 Race Street, San Jose, CA 9 512 6 l tel (40 8 ) 2 97-12 01 l

www.icst.com

LOW PHASE NOISE CLOCK MULTIPLIER

Description

The ICS601-21 is a low-cost, low phase noise, high

performance clock synthesizer for applications which

require low phase noise and low jitter. It is ICS’ lowest

phase noise multiplier. Using ICS’ patented analog and

digital Phase Locked Loop (PLL) techniques, the chip

accepts a 10 - 27 MHz crystal or clock input, and

produces output clocks up to 220 MHz at 3.3 V.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined nor guaranteed.

Features

• Fully integrated PLL, no external loop filter required

• Differential 3.3 V LVPECL outputs

• Uses fundamental 10 - 27 MHz crystal or clock

• Output clocks up to 220 MHz at 3.3 V

• Low phase noise: -122 dBc/Hz at 10 kHz

• Low jitter - 15 ps one sigma typ.

• Powerdown mode lowers power consumption

• Packaged in 16-pin TSSOP

• Advanced, low power, sub-micron CMOS process

• Operating voltage of 3.3 V

• Commercial temperature range available

Block Diagram

CLK

ROM Based

Multipliers

VCO

Divide

X1/ICLK

X2

Crystal or

clock input

Crystal

Oscillator

Reference

Divider

Phase

Comparator

VDD

Charge

Pump

Loop

Filter

VCO

S2:0

nCLK

4

GND

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ICS601-21 Datasheet(PDF) 1 Page - Integrated Circuit Systems

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