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ICS8402AYILF Datasheet(PDF) 1 Page - Integrated Circuit Systems

No. de pieza ICS8402AYILF
Descripción Electrónicos  350MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER
PDF  13 Pages
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Fabricante Electrónico  ICST [Integrated Circuit Systems]
Página de inicio  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS8402AYILF Datasheet(HTML) 1 Page - Integrated Circuit Systems

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8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS8402I is a general purpose, Crystal-to-
LVCMOS/LVTTL High Frequency Synthesizer and
a member of the HiPerClockS ™ family of High
Performance Clock Solutions from ICS. The
ICS8402I has a selectable TEST_CLK or crystal
inputs. The VCO operates at a frequency range of 250MHz
to 700MHz. The VCO frequency is programmed in steps equal
to the value of the input reference or crystal frequency. The
VCO and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic. The low
phase noise characteristics of the ICS8402I make it an ideal
clock source for Gigabit Ethernet and SONET applications.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
• (2) LVCMOS/LVTTL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 15.625MHz - 350MHz
• Crystal input frequency range: 12MHz to 40MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 30ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• -40°C to 85°C ambient operating temperature
• Lead-Free fully RoHS compliant
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N0
N1
nc
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8402I
HiPerClockS™
ICS
OSC
OE0
OE1
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
Q0
Q1
TEST
CONFIGURATION
INTERFACE
LOGIC
÷ M
0
1
0
1
PHASE DETECTOR
÷2
÷4
÷8
÷16
MR


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