PLL130-07

High Speed Translator Buffer to CMOS (Selectable Drive)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

FEATURES

• CMOS output

• Selectable Drive capability (15pF or 30pF

output load).

• Single AC coupled input (min. 100mV swing).

• Input range from DC to 200 MHz.

• 2.5V to 3.3V operation.

• Available in 8-Pin SOIC and 3x3mm QFN.

DESCRIPTION

The PLL130-07 is a low cost, high performance,

high speed, buffer that reproduces any input fre-

quency from DC to 200MHz. It provides CMOS

output with 15pF output load drive capability.

Any input signal with at least 100mV swing can

be used as reference signal. This chip is ideal

for conversion from sine wave to CMOS.

PIN CONFIGURATION

(TOP VIEW)

BLOCK DIAGRAM

Input

Amplifier

REF_IN

CLK_OUT

1

2

3

45

6

7

8

GND

REF_IN

GND

VDD

DRIV_SEL^

GND

CLK_OUT

VDD

PLL130-07

CLK_OUT

N/C

GND

VDD

12

3

4

12

11

10

9

13

14

15

16

8

7

6

5

GND

DRIV_SEL^

GND

OE^

Note: ^ denotes internal pull up