PLL130-05

High Speed Translator Buffer to PECL (Enable Low)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

FEATURES

• Differential PECL output

• Single AC coupled input (min. 100mV swing).

• Input range from DC to 1.0 GHz.

• 2.5V to 3.3V operation.

• Available in 3x3mm QFN.

DESCRIPTION

The PLL130-05 is a low cost, high performance,

high speed, buffer that reproduces any input fre-

quency from DC to 1.3GHz. It provides one pair

of differential PECL outputs. Any input signal

with at least 100mV swing can be used as refer-

ence signal. This chip is ideal for conversion

from sine wave, TTL, CMOS, or LVDS to PECL.

PIN CONFIGURATION

(TOP VIEW)

BLOCK DIAGRAM

Input

Amplifier

PECL_BAR

REF_IN

PECL

PLL130-05

PECL_BAR

PECL

GND

VDD

12

3

4

12

11

10

9

13

14

15

16

8

7

6

5

GND

GND

GND