AT25SL321 datasheet(39/82 Pages) DIALOG

No. de pieza	AT25SL321

Descripción Electrónicos	32-Mbit, 1.7 V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	82 Pages

Scroll/Zoom	100%

Fabricante Electrónico	DIALOG [Dialog Semiconductor]

Página de inicio	http://www.dialog-semiconductor.com/

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AT25SL321

DS-25SL321–112H–2020-10

8.19 64 kB Block Erase (D8h)

The Block Erase instruction is to erase the data of the selected block as being ‘1’. The instruction is used for 64K-

byte Block erase operation. Prior to the Block Erase Instruction, a Write Enable instruction must be issued. The

instruction is initiated by driving the CS pin low and shifting the instruction code D8h followed a 24-bit block

address (A23-A0). (See Figure 8-30 and Figure 8-31). The CS pin must go high after the eighth bit of the last byte

has been latched in, otherwise, the Block Erase instruction can not be executed. After CS is driven high, the self-

timed Block Erase instruction commences for a time duration of tBE2. See Section 9.8, AC Electrical

Characteristics.

While the Block Erase cycle is in progress, the Read Status Register instruction can still be read the status of

the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable

Latch (WEL) bit in the Status Register is cleared to 0.

Figure 8-30. 64 kB Block Erase Instruction (SPI Mode)

Figure 8-31. 64 kB Block Erase Instruction (QPI Mode)

AT25SL321 Datasheet(PDF) 39 Page - Dialog Semiconductor