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VS6624P0LP Datasheet(PDF) 33 Page - STMicroelectronics

No. de pieza VS6624P0LP
Descripción Electrónicos  1.3 Megapixel Mobile Camera Module
PDF  100 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VS6624P0LP Datasheet(HTML) 33 Page - STMicroelectronics

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VS6624
Data synchronization methods
Rev 1
33/100
Master / Slave operation of PLCK
In normal operation VS6624 acts as a master. PCLK is independent of the input clock
frequency and does not have a determined phase relation to the input clock.
In SLAVE operation the input clock frequency is the same as the output clock frequency and
the output data is guaranteed with a certain phase relationship to the input clock. Internally,
the VS6624 uses clocks generated from the internal PLL, but a retiming stage is used to re-
sync the output to the input clock. In this output mode, derating is not possible.



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